LTC3252EDE#TRPBF_技术文档

LTC3260

Low Noise Dual Supply

Inverting Charge Pump

FEATURES

DESCRIPTION

The LTC^®3260 is a low noise dual polarity output power

supply that includes an inverting charge pump with both

positive and negative LDO regulators. The charge pump

operatesoverawide4.5Vto32Vinputrangeandcandeliver

up to 100mA of output current. Each LDO regulator can

provide up to 50mA of output current. The negative LDO

post regulator is powered from the charge pump output.

The LDO output voltages can be adjusted using external

resistor dividers.

n

V Range: 4.5V to 31V

IN

n

Inverting Charge Pump Generates –V

IN

n

Charge Pump Output Current Up to ±00mA

n

Low Noise Negative LDO Post Regulator

–

(I

= 50mA Max)

LDO

Low Noise Independent Positive LDO Regulator

+

(I

= 50mA Max)

LDO

±00µA Quiescent Current in Burst Mode^®Operation

with Both LDO Regulators On

n

50kHz to 500kHz Programmable Oscillator Frequency

Stable with Ceramic Capacitors

Short-Circuit/Thermal Protection

Low Profile 3mm × 4mm 14-Pin DFN and Thermally

Enhanced 16-Pin MSOP Packages

The charge pump employs either low quiescent current

Burst Mode operation or low noise constant frequency

mode. In Burst Mode operation the charge pump V

regulates to –0.94 • V , and the LTC3260 draws only

100µA of quiescent current with both LDO regulators on.

In constant frequency mode the charge pump produces

an output equal to –V and operates at a fixed 500kHz

or to a programmed value between 50kHz to 500kHz us-

ing an external resistor. The LTC3260 is available in low

profile (0.75mm) 3mm x 4mm 14-pin DFN and thermally

enhanced 16-pin MSOP packages.

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

OUT

IN

APPLICATIONS

IN

n

Low Noise Bipolar/Inverting Supplies

n

Industrial/Instrumentation Low Noise Bias

Generators

n

Portable Medical Equipment

n

Portable Instruments

TYPICAL APPLICATION

LDO Rejection of V_OUTRipple

±±1V Outputs from a Single ±5V Input

+

V

12V

15V

V

LDO

IN

10mV/DIV

10µF

909k

100k

LTC3260

AC-COUPLED

+

–

+

EN

ADJ

BYP

–

V

LDO

10mV/DIV

AC-COUPLED

10nF

MODE

GND

V

OUT

10mV/DIV

+

–

100k

909k

C

BYP

AC-COUPLED

1µF

–

C

ADJ

3260 TA01b

V

= 15V

1µs/DIV

IN

–

–12V

+

–15V

V

OUT

LDO

= 12V

LDO

OSC

LDO

–

10µF

RT

= –12V

3260 TA01a

f

I

= 500kHz

= 50mA

–50mA

+

–

200k

LDO

3260f

1

LTC3260

ABSOLUTE MAXIMUM RATINGS ^{(Notes ±, 3)}

+

–

+

–

V , EN , EN , MODE.. ............................... –0.3V to 36V

V

, LDO , LDO Short-Circuit Duration........ Indefinite

IN

OUT

+

LDO ...........................................................–16V to 36V

Operating Junction Temperature Range

–

V

OUT

, LDO ............................................... –36V to 0.3V

(Note 2).................................................. –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

+

RT, ADJ ...................................................... –0.3V to 6V

BYP ......................................................... –0.3V to 2.5V

+

–

ADJ ............................................................ –6V to 0.3V

MSE Only..........................................................300°C

–

BYP ......................................................... –2.5V to 0.3V

PIN CONFIGURATION

TOP VIEW

+

EN

1

2

3

4

5

6

7

14 BYP

+

1

2

3

4

5

6

7

8

EN

RT

16 BYP

+

RT

–

13 ADJ

15 ADJ

–

BYP

12 MODE

BYP

14 MODE

–

15

17

GND

ADJ

LDO

13 EN

–

ADJ

LDO

11 EN

+

GND

12 LDO

+

10 LDO

V

11 V

10 C

OUT

IN

–

+

C

V

9

8

V

C

OUT

–

IN

+

NC

9

NC

C

MSE PACKAGE

16-LEAD PLASTIC MSOP

= 150°C, θ = 43°C/W

JA

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

DE PACKAGE

T

JMAX

14-LEAD (4mm × 3mm) PLASTIC DFN

T

= 150°C, θ = 43°C/W

JA

JMAX

EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3260EDE#PBF

LTC3260IDE#PBF

LTC3260EMSE#PBF

LTC3260IMSE#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3260EDE#TRPBF

LTC3260IDE#TRPBF

LTC3260EMSE#TRPBF

LTC3260IMSE#TRPBF

3260

–40°C to 125°C

14-Lead (4mm × 3mm) Plastic DFN

16-Lead Plastic MSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping

container.Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3260f

2

LTC3260

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 15°C (Note 1). V_IN= EN⁺= EN^–= ±1V, MODE = 0V, RT = 100kΩ.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Charge Pump

l

V

Input Voltage Range

4.5

3.4

32

4

V

IN

l

V

Undervoltage Lockout Threshold

V

IN

V

IN

Rising

Falling

3.8

3.6

V

UVLO

IN

+

–

I

V

Quiescent Current

Shutdown, EN = EN = 0V

2

5

µA

VIN

IN

–

EN = 0V, I

= 0mA

30

50

LDO

IN

+

–

MODE = V , EN = 0V, I

= I

LDO

= 0mA

80

100

3.5

160

200

5.5

µA

VOUT

+

LDO

–

MODE = V , I

MODE = 0V, I

= I

= 0mA

= I

= 0mA

µA

mA

IN VOUT

VOUT

LDO

V

RT Regulation Voltage

Regulation Voltage

1.200

V

RT

V

MODE = 12V

MODE = 0V

–0.94 • V

IN

V

OUT

–V

IN

f

Oscillator Frequency

RT = GND

450

100

0.4

500

32

550

kHz

Ω

OSC

R

Charge Pump Output Impedance

MODE = 0V, RT = GND

OUT

l

I

Max I

Short-Circuit Current

V = GND

OUT

160

1.1

1.0

0.7

250

2.0

mA

V

SHORT_CKT

VOUT

V

MODE Threshold Rising

MODE(H)

MODE(L)

MODE

MODE Threshold Falling

V

I

MODE Pin Internal Pull-Down Current

V

= MODE = 32V

µA

IN

50mA Positive Regulator

+

l

LDO Output Voltage Range

1.2

1.176

–50

50

32

1.224

50

V

+

V

ADJ

ADJ Reference Voltage

1.200

+

I

ADJ+ Input Current

V

= 1.2V

nA

ADJ

+

l

LDO Short-Circuit Current

100

0.04

0.03

400

100

1.1

mA

LDO (SC)

Line Regulation

Load Regulation

mV/V

mV/mA

mV

+

V

LDO Dropout Voltage

I

= 50mA

= 10nF

800

2.0

DROPOUT

LDO

+

Output Voltage Noise

C

µV

RMS

BYP

+

l

V

EN Threshold Rising

V

EN (H)

+

EN Threshold Falling

0.4

1.0

V

EN (L)

+

I

EN Pin Internal Pull-Down Current

V

= EN = 32V

0.7

µA

EN

IN

50mA Negative Regulator

–

l

LDO Output Voltage Range

–32

–1.224

–50

–1.2

–1.176

50

V

–

V

ADJ

ADJ Reference Voltage

–1.200

–

I

ADJ Input Current

V

= –1.2V

nA

mA

ADJ

–

l

LDO Short-Circuit Current

50

100

0.002

0.02

200

100

1.1

LDO (SC)

Line Regulation

Load Regulation

mV/V

mV/mA

mV

–

V

LDO Dropout Voltage

I

= 50mA

= 10nF

500

2.0

DROPOUT

EN(H)

LDO

–

Output Voltage Noise

C

µV

RMS

BYP

–

l

V

EN Threshold Rising

V

–

EN Threshold Falling

0.4

1.0

V

EN(L)

–

I

EN Pin Internal Pull-Down Current

V

= EN = 32V

1.4

µA

EN

IN

3260f

3

LTC3260

ELECTRICAL CHARACTERISTICS

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

The junction temperature (T , in °C) is calculated from the ambient

J

temperature (T , in °C) and power dissipation (P , in Watts) according to

A

D

the formula:

T = T + (P • θ ),

J

A

D

JA

Note 1: The LTC3260 is tested under pulsed load conditions such that

where θ = 43°C/W is the package thermal impedance.

JA

T ≈ T . The LTC3260E is guaranteed to meet specifications from

J

A

Note 3: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperatures will exceed 150°C when overtemperature protection is

active. Continuous operation above the specified maximum operating

junction temperature may result in device degradation or failure.

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3260I is guaranteed over the –40°C to 125°C operating junction

temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors.

TYPICAL PERFORMANCE CHARACTERISTICS

(T_A= 15°C, C_FLY= ±µF, C_IN= C_OUT= C_LDO⁺= C_LDO^–= ±0µF unless otherwise noted)

Oscillator Frequency

vs Supply Voltage

Oscillator Frequency vs R_T

Shutdown Current vs Temperature

600

16

14

12

10

8

600

500

400

300

R

T

= GND

500

400

V

IN

= 32V

300

200

R

T

= 200kΩ

6

200

100

0

V

= 12V

= 5V

IN

4

100

0

2

V

IN

0

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

1

10

100

(kΩ)

1000

10000

20

30

35

0

5

10

15

25

R

SUPPLY VOLTAGE (V)

T

3260 G02

3260 G03

3260 G01

Quiescent Current vs Supply

Voltage (Constant Frequency Mode)

Quiescent Current vs Temperature

(Constant Frequency Mode)

Quiescent Current vs Temperature

10

9

8

7

6

5

4

3

2

1

0

16

160

140

120

100

80

V

IN

= 12V

V

= 12V

IN

14

12

f

= 500kHz

Burst Mode OPERATION

WITH BOTH LDOs ON

OSC

10

8

f

= 500kHz

OSC

f

= 200kHz

= 50kHz

Burst Mode OPERATION

WITH NEGATIVE LDO ON

OSC

6

60

f

= 200kHz

OSC

4

40

f

= 50kHz

25

OSC

2

POSITIVE LDO ON

20

0

50 75

TEMPERATURE (°C)

5

10

20

30

35

125

100

150

–50 –25

0

25

100 125 150

0

15

–50

50

–25

0

25

75

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

3260 G04

3260 G05

3260 G06

3260f

4

LTC3260

TYPICAL PERFORMANCE CHARACTERISTICS

(T_A= 15°C, C_FLY= ±µF, C_IN= C_OUT= C_LDO⁺= C_LDO^–= ±0µF unless otherwise noted)

Voltage Loss (V_IN– |V_OUT|)

vs Output Current (Constant

Frequency Mode)

Effective Open-Loop Resistance

vs Temperature

V

_OUTShort-Circuit Current

vs Supply Voltage

250

200

150

100

50

3.0

2.5

2.0

1.5

1.0

0.5

0

60

50

40

30

20

10

0

V

= 12V

f

= 500kHz

IN

OSC

R

= GND

f

= 200kHz

T

OSC

f

= 50kHz

OSC

R

T

= 200kΩ

V

= 32V

= 25V

= 12V

IN

f

= 500kHz

OSC

0

75 100

–50 –25

0

25 50

125 150

0.1

1

10

100

0

5

10

15

20

25

30

35

TEMPERATURE (°C)

OUTPUT CURRENT (mA)

SUPPLY VOLTAGE (V)

3620 G07

3260 G09

3260 G08

LDO⁺Dropout Voltage

vs Temperature

Effective Open-Loop Resistance

vs Supply Voltage

ADJ⁺Pin Voltage vs Temperature

90

80

70

60

50

40

30

20

10

800

700

600

500

400

300

200

100

0

1.224

1.212

1.200

1.188

1.176

V

LDO

= 12V

IN

+

I

= 50mA

f

= 200kHz

= 500kHz

OSC

f

0

50 75

25

TEMPERATURE (°C)

–50 –25

0

100 125 150

0

5

10

15

30

35

–50 –25

0

25

50 75

100 125 150

20

25

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

3260 G12

3260 G10

3260 G11

LDO⁺Supply Rejection

LDO⁺GND Pin Current vs I_LOAD

LDO⁺Load Regulation

60

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

1.2006

1.2004

1.2002

1.2000

1.1998

1.1996

1.1994

V

= 12V

V

= 12V

IN

UNITY GAIN

50

40

30

20

10

0

V

I

= 6.5V

IN

+

= 5V

LDO

RIPPLE

+

= 50mA

V

= 50mV

RMS

+

C

= 10µF

LDO

0

1

10

100

0.1

1

10

100

3260 G15

0.1

1

10

FREQUENCY (kHz)

100

1000

+

I

(mA)

I

(mA)

LDO

LOAD

3260 G13

3260 G14

3260f

5

LTC3260

TYPICAL PERFORMANCE CHARACTERISTICS

(T_A= 15°C, C_FLY= ±µF, C_IN= C_OUT= C_LDO⁺= C_LDO^–= ±0µF unless otherwise noted)

LDO^–Dropout Voltage

ADJ^–Pin Voltage vs Temperature

vs Temperature

LDO^–Power Supply Rejection

60

400

350

300

250

200

150

100

50

–1.176

–1.188

–1.200

–1.212

–1.224

V

LDO

= –12V

= 50mA

OUT

–

I

50

40

30

20

10

0

V

I

= –6.5V

OUT

LDO

–

= –5V

= –50mA

V

= 50mV

RIPPLE

RMS

–

C

= 10µF

LDO

0

50 75

25

TEMPERATURE (°C)

–50 –25

0

100 125 150

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

0.1

1

10

FREQUENCY (kHz)

100

1000

3260 G18

3260 G17

3260 G16

LDO⁺Load Transient

LDO^–Load Regulation

LDO Rejection of V_OUTRipple

–1.1994

–1.1996

–1.1998

–1.2000

–1.2002

–1.2004

–1.2006

V

= –12V

OUT

UNITY GAIN

+

V

LDO

10mV/DIV

AC-COUPLED

10mV/DIV

AC-COUPLED

–

V

LDO

10mV/DIV

AC-COUPLED

V

OUT

20mA

+

10mV/DIV

I

LDO

AC-COUPLED

2mA

3260 G20

3260 G21

1µs/DIV

V

f

I

= 15V

V

= 12V

IN

40µs/DIV

IN

+

= 12V

V

= 5V

LDO

OSC

LDO

–

= –12V

= 500kHz

= 50mA

–50mA

0.1

1

10

100

+

–

I

(mA)

LDO

3260 G19

V_OUTTransient (Burst Mode

Operation, MODE = H)

V_OUTTransient

(MODE = Low to High)

LDO^–Load Transient

–

V

OUT

V

LDO

OUT

500mV/DIV

10mV/DIV

AC-COUPLED

500mV/DIV

AC-COUPLED

–5mA

–

I

MODE

OUT

–2mA

–

–50mA

I

LDO

–20mA

3260 G22

3260 G23

3260 G24

V

= 12V

LDO

REFER TO FIGURE 3

40µs/DIV

V

OSC

= 12V

2ms/DIV

V

= 12V

= 500kHz

= –5mA

2ms/DIV

IN

–

= –5V

f

= 500kHz

f

I

OSC

OUT

3260f

6

LTC3260

PIN FUNCTIONS ^(DFN/MSOP)

EN (Pin ±/Pin ±): Logic Input. A logic “high” on the EN

pin enables the positive low dropout (LDO ) regulator.

+

LDO (Pin ±0/Pin ±1): Positive Low Dropout (LDO )

Output. This pin requires a low ESR capacitor with at least

2µF capacitance to ground for stability.

+

RT (Pin 1/Pin 1): Input Connection for Programming the

–

Switching Frequency. The RT pin servos to a fixed 1.2V

EN (Pin ±±/Pin ±3): Logic Input. A logic “high” on the

–

whentheEN pinisdriventoalogic“high”.Aresistorfrom

EN pin enables the inverting charge pump as well as the

RT to GND sets the charge pump switching frequency. If

the RT pin is tied to GND, the switching frequency defaults

to a fixed 500kHz.

negative LDO regulator.

MODE (Pin ±1/Pin ±4): Logic Input. The MODE pin deter-

mines the charge pump operating mode. A logic “high”

on the MODE pin forces the charge pump to operate in

Burst Mode operation regulating V

–0.94 • V with hysteretic control. A logic “low” on the

–

BYP (Pin 3/Pin 3): LDO Reference Bypass Pin. Connect

–

a capacitor from BYP to GND to reduce LDO output

noise. Leave floating if unused.

to approximately

OUT

IN

MODE pin forces the charge pump to operate as an open-

loop inverter with a constant switching frequency. The

switching frequency in both modes is determined by an

external resistor from the RT pin to GND. In Burst Mode

operation,thisrepresentsthefrequencyoftheburstcycles

beforethepartentersthelowquiescentcurrentsleepstate.

–

ADJ (Pin 4/Pin 4): Feedback Input for the Negative Low

Dropout Regulator. This pin servos to a fixed voltage of

–1.2V when the control loop is complete.

–

LDO (Pin 5/Pin 5): Negative Low Dropout (LDO ) Linear

Regulator Output. This pin requires a low ESR (equivalent

series resistance) capacitor with at least 2µF capacitance

to ground for stability.

+

ADJ (Pin ±3/Pin ±5): Feedback Input for the Positive

+

Low Dropout (LDO ) Regulator. This pin servos to a fixed

V

(Pin 6/Pin 6): Charge Pump Output Voltage. In

voltage of 1.2V when the control loop is complete.

OUT

constant frequency mode (MODE = low) this pin is driven

+

BYP (Pin ±4/Pin ±6): LDO Reference Bypass Pin. Con-

to –V . In Burst Mode operation, (MODE = high) this pin

IN

+

nect a capacitor from BYP to GND to reduce LDO output

noise. Leave floating if unused.

voltage is regulated to –0.94 • V using an internal burst

IN

comparator with hysteretic control.

GND (Exposed Pad Pin ±5/Exposed Pad Pin ±7): Ground.

The exposed package pad is ground and must be soldered

to the PC board ground plane for proper functionality and

for rated thermal performance.

–

C (Pin 7/Pin 7): Flying Capacitor Negative Connection.

+

C (Pin 8/Pin ±0): Flying Capacitor Positive Connection.

NC(Pins8,9MSOPOnly):NoConnect.Thesepinsarenot

connected to the LTC3260 die. These pins should be left

floating, connected to ground or shorted to adjacent pins.

V (Pin 9/Pin ±±): Input Voltage for Both Charge Pump

IN

+

and Positive Low Dropout (LDO ) Regulator. V should

be bypassed with a low impedance ceramic capacitor.

IN

3260f

7

LTC3260

BLOCK DIAGRAM

Note: Pin numbers are as per DFN package. Refer to the Pin Functions section for corresponding MSOP pin numbers.

1

+

EN

INVERTING

CHARGE PUMP

+

V

C

LDO

IN

9

8

10

S1

S4

S3

S2

+

–

C

7

6

+

–

+

ADJ

13

14

V

OUT

+

BYP

1.2V

REF

50kHz

TO

500kHz

OSC

–

RT

EN

BYP

–1.2V

REF

2

3

4

–

ADJ

–

CHARGE

PUMP

AND

11

12

MODE

INPUT

LOGIC

–

LDO

5

GND

15

OPERATION ^{(Refer to the Block Diagram)}

The LTC3260 is a high voltage low noise dual output

regulator. It includes an inverting charge pump and two

LDO regulators to generate bipolar low noise supply rails

fromasinglepositiveinput.Itsupportsawideinputpower

supply range from 4.5V to 32V.

Charge Pump Constant Frequency Operation

The LTC3260 provides low noise constant frequency op-

eration when a logic low is applied to the MODE pin. The

charge pump and oscillator circuit are enabled using the

–

EN pin. At the beginning of a clock cycle, switches S1 and

+

S2 are closed. The external flying capacitor across the C

Shutdown Mode

–

and C pins is charged to the V supply. In the second

IN

In shutdown mode, all circuitry except the internal bias is

turned off. The LTC3260 is in shutdown when a logic low

phase of the clock cycle, switches S1 and S2 are opened,

while switches S3 and S4 are closed. In this configuration

+

–

+

is applied to both the enable inputs (EN and EN ). The

the C side of the flying capacitor is grounded and charge

–

LTC3260 only draws 2µA (typical) from the V supply

is delivered through the C pin to V . In steady state

IN

OUT

in shutdown.

the V

pin regulates at –V less any voltage drop due

OUT

IN

to the load current on V

or LDO.

OUT

3260f

8

LTC3260

OPERATION ^{(Refer to the Block Diagram)}

The charge transfer frequency can be adjusted between

50kHz and 500kHz using an external resistor on the RT

pin. At slower frequencies the effective open-loop output

recommended that the RT pin be tied to GND. This mini-

mizes the charge pump R , quickly charges the output

OL

up to the burst threshold and optimizes the duration of

the low current sleep state.

resistance (R ) of the charge pump is larger and it is

OL

able to provide smaller average output current (see the

Charge Pump Soft-Start

Available Output Current vs f

graph in the Typical Per-

OSC

formance Characteristics section). Figure 1 can be used

to determine a suitable value of RT to achieve a required

oscillator frequency. If the RT pin is grounded, the part

operates at a constant frequency of 500kHz.

The LTC3260 has built in soft-start circuitry to prevent

excessive current flow during start-up. The soft-start is

achievedbyinternalcircuitrythatslowlyrampstheamount

of current available at the output storage capacitor. The

soft-start circuitry is reset in the event of a commanded

shutdown or thermal shutdown.

600

500

400

Charge Pump Short-Circuit/Thermal Protection

The LTC3260 has built-in short-circuit current limit as

well as overtemperature protection. During a short-circuit

condition, the part automatically limits its output current

to approximately 160mA. If the junction temperature

exceeds approximately 175°C the thermal shutdown

circuitry disables current delivery to the output. Once

the junction temperature drops back to approximately

165°C current delivery to the output is resumed. When

thermal protection is active the junction temperature is

beyond the specified operating range. Thermal protection

is intended for momentary overload conditions outside

normal operation. Continuous operation above the speci-

fiedmaximumoperatingjunctiontemperaturemayimpair

device reliability.

300

200

100

0

1

10

100

(kΩ)

1000

10000

R

T

3260 F01

Figure ±. Oscillator Frequency vs R_T

Charge Pump Burst Mode Operation

The LTC3260 provides low power Burst Mode operation

when a logic high is applied to the MODE pin. In Burst

Mode operation, the charge pump charges the V

pin to

OUT

+

Positive Low Dropout Linear Regulator (LDO )

–0.94 • V (typical). The part then shuts down the internal

IN

+

Thepositivelowdropoutregulator(LDO )supportsaload

oscillator to reduce switching losses and goes into a low

current state. This state is referred to as the sleep state in

which the IC consumes only about 100µA with both LDOs

enabled. When the output voltage droops enough to over-

come the burst comparator hysteresis, the part wakes up

and commences charge pump cycles until output voltage

+

of up to 50mA. The LDO takes power from the V pin

IN

+

and drives the LDO output pin to a voltage programmed

+

by the resistor divider connected between the LDO , ADJ

+

and GND pins. For stability, the LDO output must be by-

passed to ground with a low ESR ceramic capacitor that

maintains a capacitance of at least 2µF across operating

temperature and voltage.

exceeds –0.94 • V (typical). This mode provides lower

IN

operating current at the cost of higher output ripple and

is ideal for light load operation.

+

TheLDO isenabledordisabledviatheEN logicinputpin.

+

When the LDO is enabled, a soft-start circuit ramps its

The frequency of charging cycles is set by the external

resistor on the RT pin. The charge pump has a lower

regulation point from zero to the final value over a period

of 75µs, reducing the inrush current on V .

R

at higher frequencies. For Burst Mode operation it is

IN

OL

3260f

9

LTC3260

OPERATION ^{(Refer to the Block Diagram)}

+

Figure 2 shows the LDO regulator application circuit.

negative by the charge pump circuitry. Soft-start circuitry

in the charge pump also provides soft-start functionality

+

The LDO output voltage V

can be programmed by

LDO

–

choosing suitable values of R1 and R2 such that:

for the LDO and prevents excessive inrush currents.

–

Figure 3 shows the LDO regulator application circuit.

R1

R2







+

V_LDO= 1.2V •

+ 1

–







The LDO output voltage V

choosing suitable values of R1 and R2 such that:

can be programmed by

LDO

An optional capacitor of 10nF can be connected from the

R1

R2







+

–

BYP pin to ground. This capacitor bypasses the internal

V_LDO= –1.2V •

+ 1







1.2V reference of the LTC3260 and improves the noise

+

performance of the LDO . If this function is not used the

When the inverting charge pump is in Burst Mode opera-

+

BYP pin should be left floating.

tion (MODE = high), the typical hysteresis on the V

OUT

–

V

pin is 2% of V voltage. The LDO voltage should be set

LTC3260

IN

–

high enough above V

in order to prevent LDO from

0

OUT

+

EN

entering dropout during normal operation.

+

LDO

OUTPUT

1

An optional capacitor of 10nF can be connected from the

C

R1

R2

OUT

+

–

ADJ

BYP

BYP pin to ground. This capacitor bypasses the internal

–1.2V reference of the LTC3260 and improves the noise

+

–

C

1.2V

REF

BYP

performance of the LDO . If this function is not used the

GND

–

BYP pin should be left floating.

3260 F02

In order to improve transient response, an optional

Figure 1: Positive LDO Application Circuit

–

capacitor, C

, may be used as shown in Figure 3. A

ADJ

–

recommended value for C

is 10pF. Experimentation

ADJ

–

Negative Low Dropout Linear Regulator (LDO )

with capacitor values between 2pF and 22pF may yield

improved transient response.

–

The negative low dropout regulator (LDO ) supports a

–

load of up to 50mA. The LDO takes power from the V

OUT

pin (output of the inverting charge pump) and drives the

LTC3260

–

GND

–1.2V

REF

LDO output pin to a voltage programmed by the resis-

–

C

–

BYP

–

BYP

ADJ

tor divider connected between the LDO , ADJ and GND

R2

R1

–

pins. For stability, the LDO output must be bypassed to

–

ADJ

ground with a low ESR ceramic capacitor that maintains a

capacitance of at least 2µF across operating temperature

and voltage.

–

LDO

1

0

OUTPUT

–

EN

C

OUT

3260 F03

–

The LDO is enabled or disabled via the EN logic input

V

OUT

–

pin. Initially, when the EN logic input is low, the charge

pump circuitry is disabled and the V

pin is at GND.

OUT

Figure 3: Negative LDO Application Circuit

–

When EN is switched high, the V

pin will be driven

OUT

3260f

10

LTC3260

APPLICATIONS INFORMATION

Effective Open-Loop Output Resistance

minimum turn-on time. The peak-to-peak output ripple at

the V

pin is approximately given by the expression:

OUT

Theeffectiveopen-loopoutputresistance(R )ofacharge

OL

pump is a very important parameter which determines the

strength of the charge pump. The value of this parameter

depends on many factors such as the oscillator frequency







I_OUT

C_OUTf_OSC

1

V_RIPPLE(P-P)

≈

– t

_ON





(f ), value of the flying capacitor (C ), the nonoverlap

OSC

FLY

where C

is the value of the output capacitor, f

oscillator frequency and t is the on-time of the oscillator

is the

OSC

OUT

time, the internal switch resistances (R ) and the ESR of

S

ON

the external capacitors.

(1µs typical).

Typical R values as a function of temperature are shown

OL

Just as the value of C

controls the amount of output

OUT

in Figure 4

ripple,thevalueofC controlstheamountofripplepresent

IN

at the input (V ) pin. The amount of bypass capacitance

60

IN

f

= 500kHz

OSC

required at the input depends on the source impedance

50

40

30

20

10

0

driving V . For best results it is recommended that V

IN

be bypassed with at least 2µF of low ESR capacitance. A

high ESR capacitor such as tantalum or aluminum will

have higher input noise than a low ESR ceramic capacitor.

Therefore, a ceramic capacitor is recommended as the

main bypass capacitance with a tantalum or aluminum

capacitor used in parallel if desired.

V

= 32V

= 25V

= 12V

IN

Flying Capacitor Selection

75 100

–50 –25

0

25 50

125 150

TEMPERATURE (°C)

The flying capacitor controls the strength of the charge

pump. A 1µF or greater ceramic capacitor is suggested

for the flying capacitor for applications requiring the full

rated output current of the charge pump.

3620 F04

Figure 4. Typical R_OLvs Temperature

Input/Output Capacitor Selection

For very light load applications, the flying capacitor may

be reduced to save space or cost. For example, a 0.2µF

capacitormightbesufficientforloadcurrentsupto20mA.

A smaller flying capacitor leads to a larger effective open-

The style and value of capacitors used with the LTC3260

determineseveralimportantparameterssuchasregulator

control loop stability, output ripple, charge pump strength

and minimum turn-on time. To reduce noise and ripple,

it is recommended that low ESR ceramic capacitors be

used for the charge pump and LDO outputs. All capacitors

should retain at least 2µF of capacitance over operating

temperature and bias voltage. Tantalum and aluminum

capacitors can be used in parallel with a ceramic capacitor

to increase the total capacitance but should not be used

alone because of their high ESR. In constant frequency

loop resistance (R ) and thus limits the maximum load

OL

current that can be delivered by the charge pump.

Ceramic Capacitors

Ceramiccapacitorsofdifferentmaterialslosetheircapaci-

tancewithhighertemperatureandvoltageatdifferentrates.

For example, a capacitor made of X5R or X7R material

will retain most of its capacitance from –40°C to 85°C

whereasaZ5UorY5Vstylecapacitorwillloseconsiderable

capacitance over that range. Z5U and Y5V capacitors may

mode, the value of C

directly controls the amount of

OUT

outputrippleforagivenloadcurrent.Increasingthesizeof

will reduce the output ripple at the expense of higher

C

OUT

3260f

11

LTC3260

APPLICATIONS INFORMATION

+

–

The flying capacitor nodes C and C switch large cur-

rents at a high frequency. These nodes should not be

routed close to sensitive pins such as the LDO feedback

also have a poor voltage coefficient causing them to lose

60% or more of their capacitance when the rated voltage

isapplied.Thereforewhencomparingdifferentcapacitors,

it is often more appropriate to compare the amount of

achievable capacitance for a given case size rather than

discussing the specified capacitance value. The capacitor

manufacture’s data sheet should be consulted to ensure

the desired capacitance at all temperatures and voltages.

Table 1 is a list of ceramic capacitor manufacturers and

their websites.

+

–

pins (ADJ and ADJ ) and internal reference bypass pins

+

–

(BYP and BYP ).

Thermal Management

At high input voltages and maximum output current, there

can be substantial power dissipation in the LTC3260. If

the junction temperature increases above approximately

175°C, the thermal shutdown circuitry will automatically

deactivate the output. To reduce the maximum junction

temperature, a good thermal connection to the PC board

groundplaneisrecommended.Connectingtheexposedpad

of the package to a ground plane under the device on two

layers of the PC board can reduce the thermal resistance

of the package and PC board considerably.

Table ±

AVX

Kemet

www.avxcorp.com

www.kemet.com

Murata

Taiyo Yuden

Vishay

www.murata.com

www.t-yuden.com

www.vishay.com

TDK

www.component.tdk.com

Derating Power at High Temperatures

Layout Considerations

To prevent an overtemperature condition in high power

applications, Figure 6 should be used to determine the

maximumcombinationofambienttemperatureandpower

dissipation.

Duetohighswitchingfrequencyandhightransientcurrents

produced by LTC3260, careful board layout is necessary

for optimum performance. A true ground plane and short

connections to all the external capacitors will improve

performanceandensureproperregulationunderallcondi-

tions. Figure 5 shows an example layout for the LTC3260.

The power dissipated in the LTC3260 should always fall

underthelineshownforagivenambienttemperature. The

power dissipated in the LTC3260 has three components.

Power dissipated in the positive LDO:

GND

+

P

= (V – V

) • I

LDO LDO

LDO

IN

Power dissipated in the negative LDO:

C

FLY

–

V

P

= (|V | – |V

|) • I

and

IN

+

OUT

–

LDO

OUT

LDO

Power dissipated in the inverting charge pump:

R

T

LDO

–

P

= (V – |V |) • (I

+ I

)

CP

IN

OUT

LDO

–

C

+

where I

denotes any additional current that might be

BYP

OUT

C

BYP

–

pulled directly from the V

pin. The LDO current is

OUT

also supplied by the charge pump through V

therefore included in the charge pump power dissipation.

and is

OUT

GND

3260 F05

The total power dissipation of the LTC3260 is given by:

Figure 5. Recommended Layout

+

–

P = P

D

+ P

LDO CP

LDO

3260f

12

LTC3260

APPLICATIONS INFORMATION

6

ThederatingcurveinFigure6assumesamaximumthermal

θ

= 43°C/W

JA

resistance, θ , of 43°C/W for the package. This can be

JA

5

4

achieved from a printed circuit board layout with a solid

ground plane and a good connection to the exposed pad

of the LTC3260 package.

THERMAL

SHUTDOWN

T = 175°C

J

3

2

It is recommended that the LTC3260 be operated in the

T = 150°C

J

region corresponding to T ≤ 150°C for continuous opera-

J

tion as shown in Figure 6. Short-term operation may be

RECOMMENDED

OPERATION

1

0

acceptablefor150°C<T <175°Cbutlong-termoperation

J

in this region should be avoided as it may reduce the life of

–50 –25

0

25 50 75 100 125 150 175

the part or cause degraded performance. For T > 175°C

AMBIENT TEMPERATURE (°C)

J

3260 F06

the part will be in thermal shutdown.

Figure 6. Maximum Power Dissipation vs Ambient Temperature

TYPICAL APPLICATIONS

Low Power ±14V Power Supply from a Single-Ended 18V Input Supply

9

10

+

24V

28V

V

LDO

IN

C4

C1

4.7µF

R1

LTC3260

4.7µF

1

1.91M

13

14

+

–

+

EN

ADJ

BYP

11

12

R2

100k

15

MODE

GND

R3

100k

8

3

4

+

–

C

BYP

C2

7

–

1µF

C

ADJ

R4

1.91M

6

5

–

–24V

V

OUT

LDO

C3

4.7µF

3260 TA02

C7

4.7µF

RT

2

High Voltage Input to Bipolar Output with Highly Efficient Dividing/Inverting Charge Pump

11

12

+

13.5V TO 32V

5V

V

LDO

IN

+

C1

4.7µF

50V

C4

4.7µF

1

13

10

R1

EN

316k

15

16

–

+

ADJ

BYP

+

R2

100k

C2

1µF

50V

C

C5

0.01µF

D1

MBR0540

LTC3260

C6

D2

R3

3

4

0.01µF

MBR0540

–

BYP

ADJ

100k

D3

MBR0540

C3

1µF

50V

R4

316k

7

5

6

–

–5V

C

LDO

C7

NOTE: THE LTC3260 WILL ALWAYS RUN

V

OUT

4.7µF

C8

4.7µF

25V

IN CONTINUOUS FREQUENCY REGARDLESS

3260 TA04

OF THE MODE PIN SETTING BECAUSE V

OUT

MODEGND RT

14 17

IS ALWAYS LESS THAN –1/2V

IN





V_IN– V – I_OUT•ROL

F

2

V_OUT~ –

– V

F





2





3260f

13

LTC3260

TYPICAL APPLICATIONS

18V Dual Tracking Bipolar Supply with Outputs from ±5V to ±15V

11

12

+

28V

OUT

V

LDO

IN

+

C1

4.7µF

50V

C3

4.7µF

35V

1

13

10

R1

EN

732k

15

16

–

+

ADJ

BYP

+

R2

73.2k

R3

500k

C

C4

C2

1µF

50V

0.01µF

LTC3260

4

3

7

–

ADJ

BYP

C

C5

0.01µF

R4

732k

14

2

5

6

–

–OUT

MODE

RT

LDO

V

C6

C7

4.7µF

50V

OUT

4.7µF

GND

17

35V

3260 TA05

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DE Package

14-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1708 Rev B)

R = 0.115

TYP

0.40 ±0.10

4.00 ±0.10

(2 SIDES)

8

14

R = 0.05

TYP

0.70 ±0.05

3.30 ±0.05

1.70 ±0.05

3.30 ±0.10

3.60 ±0.05

2.20 ±0.05

3.00 ±0.10

(2 SIDES)

PACKAGE

OUTLINE

1.70 ±0.10

PIN 1 NOTCH

R = 0.20 OR

PIN 1

0.35 × 45°

TOP MARK

(SEE NOTE 6)

CHAMFER

(DE14) DFN 0806 REV B

7

1

0.25 ±0.05

0.75 ±0.05

0.200 REF

0.25 ±0.05

0.50 BSC

3.00 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

PACKAGE OUTLINE MO-229

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3260f

14

LTC3260

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev E)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ±0.102

(.112 ±.004)

2.845 ±0.102

(.112 ±.004)

0.889 ±0.127

(.035 ±.005)

1

8

0.35

REF

5.23

(.206)

MIN

1.651 ±0.102

(.065 ±.004)

1.651 ±0.102

(.065 ±.004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

16

9

0.305 ±0.038

0.50

(.0197)

BSC

NO MEASUREMENT PURPOSE

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

RECOMMENDED SOLDER PAD LAYOUT

16151413121110

9

REF

DETAIL “A”

0.254

(.010)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0° – 6° TYP

4.90 ±0.152

(.193 ±.006)

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MSE16) 0911 REV E

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL

NOT EXCEED 0.254mm (.010") PER SIDE.

3260f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC3260

TYPICAL APPLICATION

Low Noise ±±1V Power Supply from a Single-Ended ±5V Input Supply (Frequency = 100kHz)

9

10

+

12V

15V

V

LDO

LTC3260

IN

C4

C1

10µF

R1

10µF

1

909k

13

14

+

–

+

EN

ADJ

BYP

11

+

R2

100k

C5

10nF

12

15

MODE

GND

C6

10nF

R3

100k

8

3

4

+

–

C

BYP

C2

7

–

1µF

C

ADJ

R4

909k

6

5

–

–12V

V

OUT

LDO

3260 TA03

C7

10µF

C3

10µF

RT

2

R5

200k

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

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IN

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ThinSOT Package

LTC3251

500mA Spread Spectrum Inductorless Step-Down DC/DC

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V : 2.7V to 5.5V, V : 0.9V to 1.6V, 1.2V, 1.5V, I = 9µA,

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Q

MS10E Package

LTC3252

Dual 250mA, Spread Spectrum Inductorless Step-Down DC/DC

Converter

V : 2.7V to 5.5V, V : 0.9V to 1.6V, I = 50µA,

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Q

DFN12 Package

LT1054/LT1054L

Switched-Capacitor Voltage Converters with Regulator

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3260f

LT 0412 • PRINTED IN USA

16 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2012

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3252EDE#TRPBF
厂家：	Linear Systems
描述：	LTC3252 - Dual, Low Noise, Inductorless Step-Down DC/DC Converter; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
文件：	总16页 (文件大小：360K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3252EDE#TRPBF [Linear Systems]

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